/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

module inst_fetch(
    input wire clk,
    input wire rst,
    output wire[31:0] inst_o
);

  wire[5:0] pc;
  wire rom_ce;

  pc_reg pc_reg0(.clk(clk),
                 .rst(rst),
                 .pc(pc),
                 .ce(rom_ce));

  rom rom0(.ce(rom_ce),
           .addr(pc),
           .inst(inst_o));

endmodule
